class D2DSidebandModuleIO extends Bundle
Instance Constructors
- new D2DSidebandModuleIO(fdiParams: FdiParams)
Value Members
- final def !=(arg0: Any): Boolean
- final def ##: Int
- final def :=(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
- final def <>(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
- final def ==(arg0: Any): Boolean
- def _cloneTypeImpl: Record
- def _elementsImpl: Iterable[(String, Any)]
- def _usingPlugin: Boolean
- final def asInstanceOf[T0]: T0
- macro def asTypeOf[T <: Data](that: T): T
- final macro def asUInt: UInt
- def autoSeed(name: String): D2DSidebandModuleIO.this.type
- def binding: Option[Binding]
- def binding_=(target: Binding): Unit
- def circuitName: String
- def className: String
- def clone(): AnyRef
- def cloneType: D2DSidebandModuleIO.this.type
- def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt
- final lazy val elements: SeqMap[String, Data]
- final def eq(arg0: AnyRef): Boolean
- def equals(that: Any): Boolean
- val fdiParams: FdiParams
- val fdi_lp_cfg: UInt
- val fdi_lp_cfg_crd: Bool
- val fdi_lp_cfg_vld: Bool
- val fdi_pl_cfg: UInt
- val fdi_pl_cfg_crd: Bool
- val fdi_pl_cfg_vld: Bool
- final def getClass(): Class[_ <: AnyRef]
- def getElements: Seq[Data]
- final def getWidth: Int
- def hasSeed: Boolean
- def hashCode(): Int
- def ignoreSeq: Boolean
- def instanceName: String
- final def isInstanceOf[T0]: Boolean
- def isLit: Boolean
- final def isWidthKnown: Boolean
- def litOption: Option[BigInt]
- def litValue: BigInt
- final def ne(arg0: AnyRef): Boolean
- final def notify(): Unit
- final def notifyAll(): Unit
- def parentModName: String
- def parentPathName: String
- def pathName: String
- val rdi_lp_cfg: UInt
- val rdi_lp_cfg_crd: Bool
- val rdi_lp_cfg_vld: Bool
- val rdi_pl_cfg: UInt
- val rdi_pl_cfg_crd: Bool
- val rdi_pl_cfg_vld: Bool
- val sideband_rcv: UInt
- val sideband_rdy: Bool
- val sideband_snt: UInt
- def suggestName(seed: => String): D2DSidebandModuleIO.this.type
- final def synchronized[T0](arg0: => T0): T0
- final def toAbsoluteTarget: ReferenceTarget
- final def toNamed: ComponentName
- def toPrintable: Printable
- def toString(): String
- final def toTarget: ReferenceTarget
- final def wait(arg0: Long, arg1: Int): Unit
- final def wait(arg0: Long): Unit
- final def wait(): Unit
- final def widthOption: Option[Int]
Deprecated Value Members
- def finalize(): Unit
Inherited from Bundle
Value Members
- def _elementsImpl: Iterable[(String, Any)]
- def _usingPlugin: Boolean
- def className: String
- final lazy val elements: SeqMap[String, Data]
- def ignoreSeq: Boolean
- def toPrintable: Printable
Inherited from Record
Value Members
- def _cloneTypeImpl: Record
- def cloneType: D2DSidebandModuleIO.this.type
- def getElements: Seq[Data]
- def toString(): String
Inherited from Aggregate
Value Members
- def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt
- def litOption: Option[BigInt]
- def litValue: BigInt
Inherited from Data
Value Members
- final def :=(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
- final def <>(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
- macro def asTypeOf[T <: Data](that: T): T
- final macro def asUInt: UInt
- def autoSeed(name: String): D2DSidebandModuleIO.this.type
- def binding: Option[Binding]
- def binding_=(target: Binding): Unit
- def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- final def getWidth: Int
- def isLit: Boolean
- final def isWidthKnown: Boolean
- final def widthOption: Option[Int]
Inherited from NamedComponent
Value Members
- final def toAbsoluteTarget: ReferenceTarget
- final def toNamed: ComponentName
- final def toTarget: ReferenceTarget
Inherited from HasId
Value Members
- def circuitName: String
- def equals(that: Any): Boolean
- def hasSeed: Boolean
- def hashCode(): Int
- def instanceName: String
- def parentModName: String
- def parentPathName: String
- def pathName: String
- def suggestName(seed: => String): D2DSidebandModuleIO.this.type
Inherited from AnyRef
Value Members
- final def !=(arg0: Any): Boolean
- final def ##: Int
- final def ==(arg0: Any): Boolean
- def clone(): AnyRef
- final def eq(arg0: AnyRef): Boolean
- final def getClass(): Class[_ <: AnyRef]
- final def ne(arg0: AnyRef): Boolean
- final def notify(): Unit
- final def notifyAll(): Unit
- final def synchronized[T0](arg0: => T0): T0
- final def wait(arg0: Long, arg1: Int): Unit
- final def wait(arg0: Long): Unit
- final def wait(): Unit
- def finalize(): Unit
Inherited from Any
Value Members
- final def asInstanceOf[T0]: T0
- final def isInstanceOf[T0]: Boolean
Ungrouped
- final def !=(arg0: Any): Boolean
- final def ##: Int
- final def :=(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
- final def <>(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
- final def ==(arg0: Any): Boolean
- def _cloneTypeImpl: Record
- def _elementsImpl: Iterable[(String, Any)]
- def _usingPlugin: Boolean
- final def asInstanceOf[T0]: T0
- macro def asTypeOf[T <: Data](that: T): T
- final macro def asUInt: UInt
- def autoSeed(name: String): D2DSidebandModuleIO.this.type
- def binding: Option[Binding]
- def binding_=(target: Binding): Unit
- def circuitName: String
- def className: String
- def clone(): AnyRef
- def cloneType: D2DSidebandModuleIO.this.type
- def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt
- final lazy val elements: SeqMap[String, Data]
- final def eq(arg0: AnyRef): Boolean
- def equals(that: Any): Boolean
- val fdiParams: FdiParams
- val fdi_lp_cfg: UInt
- val fdi_lp_cfg_crd: Bool
- val fdi_lp_cfg_vld: Bool
- val fdi_pl_cfg: UInt
- val fdi_pl_cfg_crd: Bool
- val fdi_pl_cfg_vld: Bool
- final def getClass(): Class[_ <: AnyRef]
- def getElements: Seq[Data]
- final def getWidth: Int
- def hasSeed: Boolean
- def hashCode(): Int
- def ignoreSeq: Boolean
- def instanceName: String
- final def isInstanceOf[T0]: Boolean
- def isLit: Boolean
- final def isWidthKnown: Boolean
- def litOption: Option[BigInt]
- def litValue: BigInt
- final def ne(arg0: AnyRef): Boolean
- final def notify(): Unit
- final def notifyAll(): Unit
- def parentModName: String
- def parentPathName: String
- def pathName: String
- val rdi_lp_cfg: UInt
- val rdi_lp_cfg_crd: Bool
- val rdi_lp_cfg_vld: Bool
- val rdi_pl_cfg: UInt
- val rdi_pl_cfg_crd: Bool
- val rdi_pl_cfg_vld: Bool
- val sideband_rcv: UInt
- val sideband_rdy: Bool
- val sideband_snt: UInt
- def suggestName(seed: => String): D2DSidebandModuleIO.this.type
- final def synchronized[T0](arg0: => T0): T0
- final def toAbsoluteTarget: ReferenceTarget
- final def toNamed: ComponentName
- def toPrintable: Printable
- def toString(): String
- final def toTarget: ReferenceTarget
- final def wait(arg0: Long, arg1: Int): Unit
- final def wait(arg0: Long): Unit
- final def wait(): Unit
- final def widthOption: Option[Int]
- def finalize(): Unit