class MainbandAfeIo extends Bundle
The mainband analog front-end (AFE) interface, from the perspective of the logical PHY layer.
All signals in this interface are synchronous to the mainband AFE's digital
clock, which is produced by taking a high speed clock from a PLL and
dividing its frequency by serializerRatio
.
With half-rate clocking (1 data bit transmitted per UI; 1 UI = 0.5 clock cycles), the PLL clock may be 2, 4, 6, 8, 12, or 16 GHz. With a serializer ratio of 16, this results in a 0.125-1 GHz AFE digital clock.
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- val pllLock: Bool
Mainband PLL Lock.
Mainband PLL Lock. Indicates whether the mainband clock is stable.
- val rxData: DecoupledIO[Vec[UInt]]
Data received on the mainband.
Data received on the mainband. Input to the async FIFO.
- val rxEn: Bool
Mainband receiver enable.
- def suggestName(seed: => String): MainbandAfeIo.this.type
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- val txData: DecoupledIO[Vec[UInt]]
Data to transmit on the mainband.
Data to transmit on the mainband. Output from the async FIFO.
- val txFreqSel: SpeedMode.Type
- final def widthOption: Option[Int]
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