class MainbandAfeIo extends Bundle

The mainband analog front-end (AFE) interface, from the perspective of the logical PHY layer.

All signals in this interface are synchronous to the mainband AFE's digital clock, which is produced by taking a high speed clock from a PLL and dividing its frequency by serializerRatio.

With half-rate clocking (1 data bit transmitted per UI; 1 UI = 0.5 clock cycles), the PLL clock may be 2, 4, 6, 8, 12, or 16 GHz. With a serializer ratio of 16, this results in a 0.125-1 GHz AFE digital clock.

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Inherited
  1. MainbandAfeIo
  2. Bundle
  3. Record
  4. Aggregate
  5. Data
  6. SourceInfoDoc
  7. NamedComponent
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new MainbandAfeIo(afeParams: AfeParams)

Value Members

  1. final def :=(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
    Definition Classes
    Data
  2. final def <>(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
    Definition Classes
    Data
  3. macro def asTypeOf[T <: Data](that: T): T
    Definition Classes
    Data
  4. final macro def asUInt: UInt
    Definition Classes
    Data
  5. def autoSeed(name: String): MainbandAfeIo.this.type
    Definition Classes
    Data → HasId
  6. def className: String
    Definition Classes
    Bundle → Record
  7. def cloneType: MainbandAfeIo.this.type
    Definition Classes
    Record → Data
  8. def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
    Definition Classes
    Data
  9. def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt
    Definition Classes
    Aggregate → Data
  10. final lazy val elements: SeqMap[String, Data]
    Definition Classes
    Bundle → Record
  11. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  12. val fifoParams: FifoParams
  13. def getElements: Seq[Data]
    Definition Classes
    Record → Aggregate
  14. final def getWidth: Int
    Definition Classes
    Data
  15. def hasSeed: Boolean
    Definition Classes
    HasId
  16. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  17. def ignoreSeq: Boolean
    Definition Classes
    Bundle
  18. def instanceName: String
    Definition Classes
    HasId → InstanceId
  19. def isLit: Boolean
    Definition Classes
    Data
  20. final def isWidthKnown: Boolean
    Definition Classes
    Data
  21. def litOption: Option[BigInt]
    Definition Classes
    Aggregate → Data
  22. def litValue: BigInt
    Definition Classes
    Aggregate → Data
  23. def parentModName: String
    Definition Classes
    HasId → InstanceId
  24. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  25. def pathName: String
    Definition Classes
    HasId → InstanceId
  26. val pllLock: Bool

    Mainband PLL Lock.

    Mainband PLL Lock. Indicates whether the mainband clock is stable.

  27. val rxData: DecoupledIO[Vec[UInt]]

    Data received on the mainband.

    Data received on the mainband. Input to the async FIFO.

  28. val rxEn: Bool

    Mainband receiver enable.

  29. def suggestName(seed: => String): MainbandAfeIo.this.type
    Definition Classes
    HasId
  30. final def toAbsoluteTarget: ReferenceTarget
    Definition Classes
    NamedComponent → InstanceId
  31. final def toNamed: ComponentName
    Definition Classes
    NamedComponent → InstanceId
  32. def toPrintable: Printable
    Definition Classes
    Bundle → Record → Data
  33. def toString(): String
    Definition Classes
    Record → AnyRef → Any
  34. final def toTarget: ReferenceTarget
    Definition Classes
    NamedComponent → InstanceId
  35. val txData: DecoupledIO[Vec[UInt]]

    Data to transmit on the mainband.

    Data to transmit on the mainband. Output from the async FIFO.

  36. val txFreqSel: SpeedMode.Type
  37. final def widthOption: Option[Int]
    Definition Classes
    Data