Type Members

1.  case class AfeParams(sbSerializerRatio: Int = 1, sbWidth: Int = 1, mbSerializerRatio: Int = 16, mbLanes: Int = 16) extends Product with Serializable
2.  class Decoupled3IO[+T <: Data] extends ReadyValid3IO[T]

   A concrete subclass of ReadyValid3IO signaling that the user expects a "decoupled" interface: 'valid' indicates that the producer has put valid data in 'bits', and 'ready' indicates that the consumer is ready to accept the data this cycle.

   A concrete subclass of ReadyValid3IO signaling that the user expects a "decoupled" interface: 'valid' indicates that the producer has put valid data in 'bits', and 'ready' indicates that the consumer is ready to accept the data this cycle. No requirements are placed on the signaling of ready or valid.

3.  class Fdi extends Bundle

   The flit-aware die-to-die interface (FDI), from the perspective of the protocol layer.

4.  case class FdiParams(width: Int = 64, dllpWidth: Int = 128, sbWidth: Int = 128) extends Product with Serializable
5.  class FifoParams extends Bundle
6.  class MainbandAfeIo extends Bundle

   The mainband analog front-end (AFE) interface, from the perspective of the logical PHY layer.

   The mainband analog front-end (AFE) interface, from the perspective of the logical PHY layer.

   All signals in this interface are synchronous to the mainband AFE's digital clock, which is produced by taking a high speed clock from a PLL and dividing its frequency by serializerRatio.

   With half-rate clocking (1 data bit transmitted per UI; 1 UI = 0.5 clock cycles), the PLL clock may be 2, 4, 6, 8, 12, or 16 GHz. With a serializer ratio of 16, this results in a 0.125-1 GHz AFE digital clock.

7.  class MainbandIo extends Bundle

   The mainband pins exposed by a standard package UCIe module in one direction.

8.  class ProtoStream extends Bundle
9.  class Rdi extends Bundle

   The raw D2D interface (RDI), from the perspective of the D2D Adapter.

10.  case class RdiParams(width: Int = 64, sbWidth: Int = 32) extends Product with Serializable
11.  abstract class ReadyValid3IO[+T <: Data] extends Bundle

    An I/O Bundle containing valid, ready, and irdy signals that handshake the transfer of data stored in the 'bits' subfield.

    An I/O Bundle containing valid, ready, and irdy signals that handshake the transfer of data stored in the 'bits' subfield.

    The base protocol implied by the directionality is that the producer uses the interface as-is (outputs bits) while the consumer uses the flipped interface (inputs bits). The actual semantics of ready/valid are enforced via the use of concrete subclasses.

12.  class Scrambler extends Module
13.  class SidebandAfeIo extends Bundle

    The sideband analog front-end (AFE) interface, from the perspective of the logical PHY layer.

    The sideband analog front-end (AFE) interface, from the perspective of the logical PHY layer.

    All signals in this interface are synchronous to the sideband clock (fixed at 800 MHz). As a result, the sideband's serializerRatio likely will be different from the mainband's serializerRatio.

14.  class SidebandIo extends Bundle

    The sideband pins exposed by a standard package UCIe module in one direction.

15.  class StandardPackageIo extends Bundle

    The pins (mainband and sideband) exposed by a standard package UCIe module in both directions.

16.  class UCIeScrambler extends Module
17.  class UnidirectionalIo extends Bundle

    The pins (mainband and sideband) exposed by a standard package UCIe module in one direction.