class Rdi extends Bundle
The raw D2D interface (RDI), from the perspective of the D2D Adapter.
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- def autoSeed(name: String): Rdi.this.type
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- def cloneType: Rdi.this.type
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- val lpClkAck: Bool
- val lpConfig: Valid[UInt]
- val lpConfigCredit: Bool
- val lpData: Decoupled3IO[UInt]
Adapter to Physical Layer data.
Adapter to Physical Layer data.
Encompasses lp_irdy, lp_valid, and pl_trdy from the UCIe specification.
- val lpLinkError: Bool
Adapter to Physical Layer indication that an error has occurred which requires the Link to go down.
Adapter to Physical Layer indication that an error has occurred which requires the Link to go down. Physical Layer must move to LinkError state and stay there as long as lp_linkerror=1. The reason for having this be an indication decoupled from regular state transitions is to allow immediate action on part of the Adapter and Physical Layer in order to provide the quickest path for error containment when applicable (for example, a viral error escalation must map to the LinkError state). The Adapter must OR internal error conditions with lp_linkerror received from Protocol Layer on FDI.
- val lpRetimerCrd: Bool
When asserted at a rising clock edge, it indicates a single credit return from the Adapter to the Physical Layer for the Retimer Receiver buffers.
When asserted at a rising clock edge, it indicates a single credit return from the Adapter to the Physical Layer for the Retimer Receiver buffers. Each credit corresponds to 256B of mainband data. This signal must NOT assert for dies that are not UCIe Retimers.
- val lpStallAck: Bool
- val lpStateReq: PhyStateReq.Type
Adapter request to Physical Layer to request state change.
- val lpWakeReq: Bool
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- val plClkReq: Bool
- val plConfig: Valid[UInt]
- val plConfigCredit: Bool
- val plCorrectableError: Bool
- val plData: Valid[UInt]
Physical Layer to Adapter data.
Physical Layer to Adapter data.
Encompasses
pl_validandpl_datafrom the UCIe specification. Note that backpressure is not possible. Data should be sampled whenever valid is asserted at a clock edge. - val plError: Bool
- val plInbandPres: Bool
- val plLinkWidth: PhyWidth.Type
- val plNonFatalError: Bool
- val plPhyInRecenter: Bool
- val plRetimerCrd: Bool
When asserted at a rising clock edge, it indicates a single credit return from the Retimer to the Adapter.
When asserted at a rising clock edge, it indicates a single credit return from the Retimer to the Adapter. Each credit corresponds to 256B of mainband data. This signal must NOT assert if the remote Link partner is not a Retimer.
- val plSpeedMode: SpeedMode.Type
- val plStallReq: Bool
- val plStateStatus: PhyState.Type
Physical Layer to Adapter Status indication of the Interface.
Physical Layer to Adapter Status indication of the Interface.
The status signal is permitted to transition from Physical Layer autonomously when applicable. For example the Physical Layer asserts the Retrain status when it decides to enter retraining either autonomously or when requested by remote agent.
- val plTrainError: Bool
- val plWakeAck: Bool
- def suggestName(seed: => String): Rdi.this.type
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