class SidebandAfeIo extends Bundle
The sideband analog front-end (AFE) interface, from the perspective of the logical PHY layer.
All signals in this interface are synchronous to the sideband clock (fixed
at 800 MHz). As a result, the sideband's serializerRatio likely will be
different from the mainband's serializerRatio.
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- val pllLock: Bool
Sideband PLL Lock.
Sideband PLL Lock.
Indicates whether the sideband clock is stable.
- val rxClock: Bool
- val rxData: UInt
Data received on the sideband.
Data received on the sideband.
Input to the async FIFO.
- val rxEn: Bool
Enable sideband receivers.
- def suggestName(seed: => String): SidebandAfeIo.this.type
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- val txClock: Bool
- val txData: UInt
Data to transmit on the sideband.
Data to transmit on the sideband.
Output from the async FIFO.
- final def wait(arg0: Long, arg1: Int): Unit
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